An Adaptive Approximation Method for Traffic Reduction in Network on Chip

By technology scaling, Network-on-Chips (NoCs), which have been accepted as a promising on-chip communication in many-core systems, face high network latency and excessive power consumption. Data-intensive applications possess a large amount of data transmission in the network which imposes high network latency and power consumption. An innovative method is required to address the heavy traffic in the network. These applications can tolerate some output errors, which opens a new communication mechanism. Therefore, the approximation technique can be employed to decrease network congestion, and achieve high performance and high energy-saving. In this paper, a new approach is proposed in which the transmitted packet size is reduced by traversing the approximate differences between the packets. This approach reduces traffic volume in NoCs based on the data locality and the error tolerance of the applications without any significant quality reduction in the application output. This technique is applied in 3D NoC architecture to profit its lower latency compared to 2D NoC. Thus, it reduces the latency and power consumption in three dimensional Network-on-Chip (3D NoC), which alleviates 3D NoC thermal challenges. The simulation results indicate that the proposed approximate communication reduces the latency and dynamic power consumption by 41% and 44% compared to baseline 3D NoC, respectively.