A 1.4-Pj/B, Power-Scalable 16x12-Gb/S Source-Synchronous I/O With Dfe Receiver In 32nm Soi Cmos Technology

Timothy O. Dickson,Yong Liu,Sergey V. Rylov,Ankur Agrawal,Seongwon Kim,Ping-Hsuan Hsieh,John F. Bulzacchelli,Mark Ferriss,Herschel Ainspan,Alexander Rylyakov,Benjamin D. Parker,Christian Baks,Lei Shan,Young Kwark,Jose Tierno,Daniel J. Friedman

2014 IEEE PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)（2014）

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摘要

A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels. Measurements of a test chip fabricated in 32nm SOI CMOS technology demonstrate 1.4-pJ/b efficiency over 0.75 '' Megtron-6 PCB traces, and 1.9-pJ/b efficiency over 20 '' Megtron-6 PCB traces.

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