Noise and Linear Distortion Analysis of Analog/RF Performance in a Two Dimensional Dielectric Pocket Junctionless Double Gate (DP-JLDG) MOSFET to Control SCEs

In this paper, a dielectric pocket junctionless double gate (DP-JLDG) MOSFET has been proposed with an example of n-channel and with a 20 nm channel length. The characteristics of the proposed device have been compared with a junctionless double gate (JLDG) MOSFET. The proposed device offers excellent analog/RF behavior and can operate over a wide range of frequency with low power dissipation. This paper also analyses the impact of dielectric pockets on analog and digital performance of the device. Further, in this paper an exclusive effort to investigate the noise and distortion analysis of DP-JLDG MOSFET has been incorporated. The proposed device is an appropriate alternative for low power analog and digital circuits due to its higher device gain, larger operating range, and lower power dissipation.