An 8-Channel 4.5gb 180gb/S 18ns-Row-Latency Ram For The Last Level Cache
Tah-Kang Joseph Ting, Gyh-Bin Wang,Ming-Hung Wang,Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh,Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang,Chi-Kang Chen,Yung-Fa Chou,Ding-Ming Kwai, Zhe Wang,Wei Wu,Shigeki Tomishima, Pat Stolt,Shih-Lien Lu 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)（2017）
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