A P-V-N Diode Model For Cmos Latchup

A fully analytic model for holding voltage in a CMOS latch structure is derived by representing the device as a p-i-n or p-nu-n diode. Due to heavy conductivity modulation in the region between emitters, this representation corresponds more closely to reality than lumped bipolar circuit equivalents, and requires no characterization of the parasitic latch components. Through considerations of the various current flows through the latch, an expression for the holding voltage as a function of emitter-emitter spacing is derived. Comparison with numerical simulation indicates adequate agreement.