Evaluation Of Stt-Mram L3 Cache In 7nm Finfet Process

The performance and power of the memory system cannot gradually follow the improving speed and power of the computational cores. To improve the memory performance, the L3 cache implemented with SRAM is generally used. However, the SRAM - is not suitable for L3 cache, which has a low access rate (about 0.01%) and a large capacity (tens of MB) because the SRAM - L3 cache has large area and consumes significant amount of leakage power. The STT-MRAM which is a next-generation memory, has a smaller cell area and very lower leakage power than that of SRAM. However, STT-MRAM is slower than SRAM - in read and write operations, but it is fast enough to be used in the L3 cache. In this paper, we evaluate the STT-MRAA/I L3 cache by comparing with the SRAM - L3 cache in 7nm FinFET process which maximizes the performance and integration of cores. Compared to the SRAM L3 cache, the STT-MRAM L3 cache has 50% smaller area, consumes 95% smaller leakage power. Although STT-MRAM has penalties in read/write latency and dynamic energies, these problems can be ignored because of low access rate of L3 cache. Therefore, it is attractive to replace the SRAM - with ultra-low leakage STT-MRAM for L3 cache.