Fast buffered clock tree synthesis in multi corner multi mode scenario
2018 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC)(2018)
摘要
As CMOS technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in high-performance synchronous chip design. Recently, the process variation during manufacturing affects the performance of the circuit design. In this paper, we proposed fast buffered clock tree synthesis (FBCTS) in multi-corner multi-mode (MCMM) scenario. The ISPD '09 benchmark is used to verify the proposed method. The experiment results show our method reduce about 59% of computation time compared to existing method.
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关键词
skew,process variation,MCMM,DME,CTS
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