Processor Architecture Optimization for Spatially Dynamic Neural Networks
2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)(2021)
摘要
Spatially dynamic neural networks adjust network execution based on the input data, saving computations by skipping non-important image regions. Yet, GPU implementations fail to achieve speedups from these spatially dynamic execution patterns for most neural network architectures. This paper investigates hardware constraints preventing such speedup and proposes and compares novel processor archite...
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关键词
Spatial dynamic execution,processor design,analytic modelling,scheduling optimizer
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