Processor Architecture Optimization for Spatially Dynamic Neural Networks

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)(2021)

引用 2|浏览6
暂无评分
摘要
Spatially dynamic neural networks adjust network execution based on the input data, saving computations by skipping non-important image regions. Yet, GPU implementations fail to achieve speedups from these spatially dynamic execution patterns for most neural network architectures. This paper investigates hardware constraints preventing such speedup and proposes and compares novel processor archite...
更多
查看译文
关键词
Spatial dynamic execution,processor design,analytic modelling,scheduling optimizer
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要