Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

We introduce a scalable hardware architecture for large-scale invertible logic. Invertible logic has been recently presented that can realize bidirectional computing probabilis-tically based on Hamiltonians with a small number of non-zero elements. In order to store and compute the Hamiltonians efficiently in hardware, a sparse matrix representation of PTELL (partitioned and transposed ELLPACK) is...