An Ultra-wideband Limiting Amplifier for 15Gbps Receiver of JESD204B Physical Layer.

SerDes receivers are widely used in data converters and limiting amplifiers are widely used in the SerDes receivers. The paper presents the design of an ultra-wideband limiting amplifier applied to the receiver of JESD204B physical layer. This limiting amplifier adopts Current Mode Logic (CML) structure composed of three third-order stages for achieving the ultra-wide bandwidth with high gain. Feedback structure techniques, negative Miller capacitance techniques and inductor peaking techniques are implemented, which further increase bandwidth. On the other hand, this limiting amplifier could achieve equalizing easily for compensating for different channel loss. This limiting amplifier could work at the bit-rate of 15Gbps which fully reaches the highest data rate specified in the JESD204B standard. This limiting amplifier occupies area of 0.03mm2 and consumes a power of 21.6mW with a supply voltage 1.2V in TSMC 65nm CMOS technology.