A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics.
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)（2021）
Key words
DRAM interface,quadrature error corrector (QEC),duty-cycle error correction (DCC),digital loop filter (DLF),successive approximation register (SAR),re-lock
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