A 1.4-V-ppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC)(2021)

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摘要
This article develops a high-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) implemented in a 28-nm CMOS process. The proposed 4-tap hybrid feed-forward equalization (FFE) employs the fractionally-spaced pre-emphasis (FS-PE) and the baud-spaced de-emphasis (BS-DE). The PE-based FFE enlarges the output swing by directly stacking the distorted pulses, and it naturally consumes less power as it only boosts the desired distorted symbols. Additionally, the FS-based FFE provides a compensation for high-frequency loss beyond f (Nyquist) and the post2 tap equalizes the low-frequency channel loss, which could match the chan-nel attenuation accurately. Combining both the FS-PE-based pre/postl taps and BS-DE-based post2 tap, the proposed TX achieves a differential output swing of 1.4 V-ppd and an energy efficiency of 1.53 pJ/bit, and the eye height and eye width are 198 mV and 0.48 UI at the data rate of 64 Gb/s.
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