Area and Cost Analysis of the Mixed Signal Circuits in a Novel Monolithic 3D Process

This paper discusses the mixed-signal circuit design in a novel monolithic (sequential) 3D process. The goal of this work is to explore a novel multi-process sequential 3D technology with the state-of-art 3D interconnections density of 2 x 10(7) via/mm(2) and we report our first impressions. The paper discusses the design of a 3-bit SAR and a 3-bit Flash ADCs, where we have partitioned digital and analog parts in a new under test shrink 65nm technology stacked over a 28nm FDSOI process. The 3D connection density of the applied process is almost on par with the horizontal connection densities within a tier. This fact will enable what we refer to as 'Systems-in-Cube' (SinC), i.e. fine-grained volume implementations where individual transistor of small functional blocks can be distributed across 3D tiers. We estimate an area reduction of about 40% compared to a pure 2D 28nm realization of the same circuits and 80% compared to an equivalent 2D 65nm implementation for a 'balanced' mixed signal design. Moreover, we also estimate that this would result in an overall price reduction for these circuits in a mature commercial sequential 3D process.