A Fast Settling Frequency Synthesizer With Switched-Bandwidth Loop Filter

This paper presents a new method to substantially decrease the settling time of analog phase-locked loops (PLLs) while keeping its phase noise unaffected. This is achieved by switching the loop filter capacitors and resistor in such a way that output frequency is kept seamless. This method only affects the loop filter architecture and does not need any other changes to other blocks of the PLL. A frequency synthesizer circuit is implemented to validate the proposed method. The reference synthesizer has a 342-mu s settling time for a 1-GHz frequency step (1.5 to 2.5 GHz), while if the proposed technique is enabled, the settling time is reduced to 48 mu s (worst case). The measured phase noise of the synthesizer at 10-kHz offset from a 2-GHz carrier is -110 dBc/Hz.