SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling

Keonhee Cho,Heekyung Choi,In Jun Jung,Ji Sang Oh,Tae Woo Oh,Ki-Ryong Kim,Giseok Kim,Taemin Choi,Changsoo Sim,Taejoong Song,Seong-Ook Jung

2021 Symposium on VLSI Circuits（2021）

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摘要

This paper presents SRAM write- and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.

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关键词

interconnect resistance effects,technology scaling,bit-cell compatible layouts,bit-cell array,SRAM write-assist cells,performance-assist cells,write-ability degradation

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