Memristive Stateful Logic With N-Modular Redundancy Error Correction Design Towards High Reliability

Although the memristive stateful logic is a promising candidate to implement energy-efficient edge computing, the reliability is still a big challenge. This work aims to analyze the reliability of memristive stateful logic, and proposes an n-modular redundancy method for error correction. Such design could efficiently increase the successful operation rate without an additional CMOS logic gate. The application of a 1-bit full adder (FA) is demonstrated as a feasibility example of validation.