High Resolution Time-to-Digital Converter Design with Anti-PVT-Variation Mechanism
2021 IEEE 4th International Conference on Electronics Technology (ICET)(2021)
摘要
This paper presents a 5.4-ps resolution with anti-PVT-variation Time-to-Digit Converter (TDC) using 90-nm CMOS technology. This proposed TDC uses the two-step architecture in which the first stage is Buffer Delay line to get a wide dynamic range and then the delayed start and stop signals are given to the second stage (Vernier Delay line) by an edge detector for higher resolution. This whole two-s...
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关键词
Temperature sensors,Temperature measurement,Image edge detection,Detectors,Resists,Dynamic range,Delay lines
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