Comparison Of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs

This paper presents a detailed comparison between the two commonly used capacitive DAC architectures for 10-bit SAR ADCs: binary-weighted and split-capacitor DACs. These DAC architectures are compared based on the impact of unit-capacitor mismatch and parasitic capacitance on their linearity, area and power consumption. The split-capacitor DAC is shown to be much more sensitive to unit-capacitor mismatch and parasitic capacitances as opposed to the binary-weighted DACs. Unit-capacitor values are then calculated for the split-capacitor and binary-weighted DAC topologies under two orthogonal scenarios: (a) Fixed linearity at the expense of the area and power consumption and (b) Maximizing the linearity within a specified area budget. In-spite of requiring significantly lower number of unit elements as compared to a binary-weighted DAC, split-capacitor DAC yields a larger value of unit-capacitor and total DAC capacitance for fixed linearity scenario and conversely results in a lower effective number of bits (ENOB) for a fixed area specification. Based on our analysis, binary DAC is found to be more area and power efficient than its split capacitor counterpart.