State-Of-The-Art Circuit Techniques For Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark Fom Based On An Extensive Survey

A conventional figure-of-merit for a phase-locked loop (PLL) based on integrated RMS jitter and power consumption has been a strong indicator to compare and to normalize PLL performance over different designs. However, it has some limitations because any impact from reference clock is not reflected. As a result, it is not enough to evaluate state-of-the-art PLL designs such as injection-locked PLL, clock-multiplying delay-locked loop, and sub-sampling PLL where PLL circuit noise is effectively suppressed so the reference clock contributes more on PLL jitter performance. This paper discusses alternative figure-of-merits capturing the reference clock impacts based on an extensive survey of state-of-the-art PLL designs, and also validates them with the survey.