A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS

This paper presents a 2-bit/cycle 2-step hybrid successive-approximation-register (SAR) analog-to-digital converter (ADC) with 6-bit resolution. A latch consisting of dynamic logic gates is proposed to speed up the ADC conversion process and largely enhance the power efficiency. Furthermore, in the 2-step structure, the logic of the two-stage ADC is modified, and the capacitance arrays of the DACs are accordingly adjusted so that the performance of each stage is optimized. Designed and simulated in a 65-nm CMOS technology, the proposed single channel ADC achieves SNDR and SFNR of 36.76 and 46.89 respectively, resulting in 5.8 ENOB, the THD is -42.22dB, SNR is 38.22 dB, and FoM at Nyquist rate is 85.9 fJ/conversion-step. The total power consumption of the ADC is 8.6 mW at a sampling rate up to 1.8 GS/s.