Sub 20 nm‐Node LiNbO 3 Domain‐Wall Memory

Conducting domain walls (DWs) induced by an in-plane electric field applied to a mesa-like cell fabricated at the surface of an insulating LiNbO3 single-crystal film play a key role in the diode-like DW memory. However, the lateral shrinking of the cell size below a 20 nm-node technology becomes challenging due to the presence of interfacial layers with the finite thickness above 30 nm. In this work, 15 nm-sized LiNbO3 cells are fabricated in high on/off current ratio of approximate to 10(2) on the SiO2/Si wafers immune to the interfacial-layer effect, which can be operated below 5 V and also promising to meet the CMOS processing. It is found that the interfacial-layer thickness reduces almost linearly with the shrinking cell size from 100 to 15 nm and the DW current increases by 25 times. The retention time of written information at +/-3 V is over 48 h, the domain switching time can approach 5 ns at 4 V in high switching endurance (approximate to 10(9) cycles). These achievements imply the high storage density of a ferroelectric DW memory without the fundamental interfacial-layer limit.