Timing Critical Path Validation for Intel ATOM Cores Using Structural Test
2021 IEEE 39th VLSI Test Symposium (VTS)(2021)
摘要
This paper describes a novel methodology of creating scan-based at-speed structural patterns to analyze and validate functional critical paths on latch-based high performance CPU cores. Silicon data comparison with traditional transition fault patterns and functional patterns are conducted and reported to illustrate the effectiveness of the proposed scheme.
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关键词
Snow,Very large scale integration,Silicon,Timing,Test pattern generators
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