Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts

2021 IEEE 39th VLSI Test Symposium (VTS)(2021)

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摘要
Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases in test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted by DC tests. Recent research has shown the need for multi-pattern tests where intermediate defect resistance values are concerned, as opposed to extrem...
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关键词
Resistance,Industries,Simulation,Integrated circuit interconnections,Logic gates,Very large scale integration,Delays
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