An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique

2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)(2021)

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摘要
This paper presents an 8-bit 1.25GS/s folding-subrange ADC, implemented in 65nm CMOS technology. We design a coarse comparator to relieve critical metastability issue. A latch sharing technique in fine comparator can further reduce area overhead. Operating at 1.25GHz sampling rate with low input frequency, the measured SFDR and SNDR are 56.5dB and 43.4dB, respectively. When split-then-share buffer...
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关键词
Time-frequency analysis,Latches,Design automation,Bit error rate,Oscilloscopes,Very large scale integration,Frequency measurement
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