Fast Binary Counters and Compressors Generated by Sorting Network
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2021)
摘要
The summation of multiple operands in parallel forms part of the critical path in various digital signal processing units. To speedup the summation, high compression ratio counters and compressors are necessary. In this article, we present a novel method of fast saturated binary counters and exact/approximate (4:2) compressors based on the sorting network. The inputs of the counter are asymmetrica...
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关键词
Sorting,Compressors,Delays,Stacking,Logic gates,Adders,Image coding
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