A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process
2020 IEEE International Electron Devices Meeting (IEDM)(2020)
摘要
In this paper, we present the design and silicon characterization results of an 8Mb STT-MRAM macro in 16nm FinFET Logic CMOS process. The STT-MRAM film stack is carefully designed to achieve both solder-reflow tolerance and short write pulse of 50nS. A merged reference scheme with reverse connected reference cells are proposed for read-disturb immunity. A read access time of 9nS is achieved from -40C to 125C and Vdd=0.8V±10%, making it suitable for high performance MCU applications. Silicon data measurement is presented to demonstrate a logic-process compatible, perpendicular STT-MRAM in 16nm FinFET CMOS process. The bit-error-rate has achieved zero fail-bit-count at 50-percentile for the 8Mb test-chip at wafer level.
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关键词
silicon characterization results,STT-MRAM macro,STT-MRAM film stack,solder-reflow tolerance,reverse connected reference cells,read-disturb immunity,read access time,FinFET Logic CMOS process,short write pulse,size 16.0 nm
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