Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium

V. Vega-Gonzalez,H. Puliyalil,J. Versluijs,A. Lesniewska, O. Varela-Pereira,R. Baert,S. Paolillo,S. Decoster,F. Schleicher,D. Montero,J. Bekaert,E. Kesters,Q. T. Le,C. Lorant,L. Teugels,N. Heylen,N. Jourdan,Z. El-Mekki,M. van der Veen,I Ciofi,B. Briggs,J. Heijlen, L. Dupas,B. De-Wachter,E. Vancoille,T. Webers, H. Vats,L. Rynders,M. Cupak,J. Uk-Lee,Y. Drissi, L. Halipre,A-L Charley,P. Verdonck,T. Witters, S. Gompel,Y. Kimura, I Demonie,F. Lazzarino,M. Ercken,R. Kim,D. Trivkovic,K. Croes,P. Leray,M. Jaysankar,C. Wilson, G. Muroch,Z. Tokei

2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2020）

引用 3|浏览10

关键词

supervia process integration,stacked vias,barrierless ruthenium,high-aspect-ratio,place-and-route simulations,Power Delivery Network,IR-drop reduction,thermal shock tests,SV failure,time-dependent-dielectric-breakdown,PnR simulations,TDDB tests,temperature -50.0 degC to 125.0 degC,time 250.0 hour,size 3.0 nm,size 21.0 nm,Ru

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