Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming

Latches have the advantages of timing-borrowing, smaller cell area, lower input capacitance, and lower power compared to flip-flops (FFs). This article presents a CAD flow that converts any arbitrarily complex single-clock-domain FF-based RTL design into an efficient 3-phase latch-based design. The flow includes a novel 3-phase aware retiming algorithm for power and area optimization. Post place-a...