A High-Density Logic-on-logic 3DIC Design Using Face-to-face Hybrid Wafer-Bonding on 12nm FinFET Process

S. Sinha, S. Hung, D. Fisher,X. Xu, C. Chao, P. Chandupatla, F. Frederick, H. Perry,D. Smith,A. Cestero,J. Safran, V Ayyavu,M. Bhargava,R. Mathur,D. Prasad, R. Katz, A. Kinsbruner,J. Garant,J. Lubguban,S. Knickerbocker, V Soler,B. Cline,R. Christy, T. McLaurin,N. Robson,D. Berger

2020 IEEE International Electron Devices Meeting (IEDM)（2020）

引用 14|浏览36

关键词

wafer-bond nets,multiple wafer-bonded pairs,face-to-face hybrid wafer-bonding,FinFET process,synchronous cache coherent mesh interconnect design,industry tool compatible innovative physical implementation flow,3D aggregate bandwidth,bandwidth density,face-to-face wafer-bond 3D connections,industry demonstration,high-density logic-on-logic 3D IC design,3D IC design-for-test standard,high-density-3D test-vehicle,Arm Neoverse CMN-600,EEE 1838 3DIC design-for-test standard,DFT standard,3D-stacked dies,data analysis,power-delivery 3D wafer-bond nets,3D-stacked high performance logic-on-logic applications,energy efficiency,size 12.0 nm,bit rate 307 Gbit/s

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