3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

C. J. Su,M. K. Huang, K. S. Lee,V. P. H. Hu, Y. F. Huang, B. C. Zheng, C. H. Yao,N. C. Lin,K. H. Kao,T. C. Hong,P. J. Sung,C. T. Wu, T. Y. Yu,K. L. Lin,Y. C. Tseng,C. L. Lin,Y. J. Lee,T. S. Chao,J. Y. Li,W. F. Wu,J. M. Shieh,Y. H. Wang,W. K. Yeh

2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2020）

引用 10|浏览29

关键词

3D integration,vertical stacking,embedded RRAM,CMOS inverter,pFET,enhanced resistive switching endurance,integrated 2D materials,embedded 2T1R configuration,surface modification,CMOS-based bipolar RRAM 1T1R,CMOS-based bipolar RRAM 2T1R,3D embedded logics,Ti-MoS2-Si

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要