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First Demonstration of Heterogenous Complementary FETs Utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

T-Z Hong,W-H Chang,A. Agarwal,Y-T Huang,C-Y Yang,T-Y Chu, H-Y Chao,Y. Chuang,S-T Chung,J-H Lin, S-M Luo,C-J Tsai,M-J Li,X-R Yu,N-C Lin,T-C Cho,P-J Sung,C-J Su,G-L Luo,F-K Hsueh,K-L Lin,H. Ishii,T. Irisawa,T. Maeda,C-T Wu,W. C-Y Ma,D-D Lu,K-H Kao,Y-J Lee, H. J-H Chen,C-L Lin,R. W. Chuang,K-P Huang,S. Samukawa,Y-M Li,J-H Tarng,T-S Chao,M. Miura,G-W Huang,W-F Wu,J-Y Li,J-M Shieh,Y-H Wang,W-K Yeh

2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2020）

Cited 19|Views40
Key words
low-temperature hetero-layers bonding technique,layer transfer technique,multichannel structure,wafer-scale LT-HBT,heterogenous complementary FET,3D channel stacking integration,surface activating chemical treatment,ultimate device footprint scaling,temperature 200.0 degC,temperature 293.0 K to 298.0 K,Ge,Si
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