Demonstration of narrow switching distributions in STT-MRAM arrays for LLC applications at 1x nm node

E. R. J. Edwards,G. Hu,S. L. Brown, C. P. D'Emic,M. G. Gottwald,P. Hashemi, H. Jung,J. Kim, G. Lauer,J. J. Nowak,J. Z. Sun, T. Suwannasiri,P. L. Trouilloud,S. Woo,D. C. Worledge

international electron devices meeting（2020）

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摘要

We demonstrate spin-transfer torque magnetoresistive random access memory (STT-MRAM) arrays achieving 2.8e-10 write error rate (WER) performance at 3 ns write duration at a magnetic tunnel junction (MTJ) diameter of 40 nm. The bit-to-bit distribution of the write voltage at a WER of 1e-6 is characterized by a relative standard deviation of 3.7% for W0 and 4.5% for W1, sufficient to meet the write voltage distribution requirement for last-level cache (LLC) applications at 1x nm nodes.

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关键词

narrow switching distributions,STTMRAM arrays,LLC applications,spin-transfer torque magnetoresistive random access memory,error rate performance,WER,magnetic tunnel junction diameter,bit-to-bit distribution,relative standard deviation,write voltage distribution requirement,last-level cache applications,write duration,MTJ diameter,time 3.0 ns,size 40.0 nm

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