A 10-b 500MS/s Partially Loop-unrolled SAR ADC with a Comparator Offset Calibration Technique

This paper presents a 10-b 500MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) designed using a 40nm CMOS process. The first 6-bit coarse conversion is completed by a high speed loop–unrolled architecture, while the succeeding 5 bits are obtained by a traditional SAR structure. A foreground calibration is employed to correct the offsets in the six comparators of the c...