Reconfigurable single instruction multiple data and systolic array structure, processor and electronic terminal

The invention provides a reconfigurable single instruction multiple data and systolic array structure, a processor and an electronic terminal. The single instruction multiple data and systolic array structure comprises multiple processing engines and multiple data output channels, wherein the processing engines are distributed in a systolic array, an operand collector is correspondingly connectedto each processing engine, and each processing engine is connected with the adjacent processing engine; the data output channels are correspondingly configured at the tops of all lines of processing engines, the data output channel of the top of each line is connected with the first processing engine of the corresponding line, and all the data output channels are further connected with the processing engines at the rightmost sides of all rows of processing engines in a one-to-one corresponding mode. The processor which is reconfigurable and low in energy consumption, and integrates single instruction multiple data (SIMD) and the systolic array is achieved, and the lower energy consumption is achieved by building transmission channels between every two adjacent processing engines and multi-level storage optimization.