A statistical study into reliability of FPGA implemented circuits: Simulation and modelling

In this work, we report on the development of a methodology to study the reliability of digital circuits implemented in FPGA. For this, the design and simulation tools have been extended to introduce aging. The aging laws for Look-Up Tables, describing the drifts in the propagation time, caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms, have been integrated into the simulation environment by introducing additional variables and equations. Moreover, the study has been further extended by considering the statistical dispersion in the failure time due to different sources of dispersion. Furthermore, an analytical and a statistical model of the failure time of the digital circuit as a function of the clock frequency, aging law parameters and dispersion parameters have been proposed. Finally, the developed methodology has been applied to two different digital circuits implemented in FPGA.