A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers

A half-rate jitter-tolerant referenceless digital clock and data recovery (D-CDR) circuit for cellular transceivers is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Also, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust a phase of the recovered clock. Fabricated in 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.