fT Improvement of RF CMOS Transistor in Circuit-Level by Layout Optimization

Zhi-Jian Chen,Peng-Cheng Huang,Bin Li,Yu-Chen Wang,Xiao-Ling Lin,Hong Chen

international conference on solid state and integrated circuits technology（2020）

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摘要

In this paper, $f_{T}$ improvement of radio-frequency (RF) CMOS transistor in circuit-level by layout optimization has been presents. A new layout optimization scheme to reduce the interconnect parasitic of multi-finger MOSFETs is present in this paper. The devices characterized are simulated by a 55-nm RF CMOS process model. The post-simulation shows that the $f_{T}$ performance improves 24.4% at 80GHz. And the proposed optimization of the RF MOS layout can significantly improve the S21 and NF characteristics of the low noise amplifier (LNA).

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关键词

RF MOS layout,RF CMOS transistor,circuit-level,radio-frequency CMOS transistor,layout optimization scheme,interconnect parasitic,multifinger MOSFET,RF CMOS process model,fT improvement,low noise amplifier,LNA,frequency 80.0 GHz,size 55 nm

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