Process Conditions For Low Interface State Density In Si-Passivated Ge Devices With Tmsio Interfacial Layer
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY(2020)
摘要
In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 degrees C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for D-it < 510(11) cm(-2) eV(-1). Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 310(11) eV(-1) cm(-2) and a significant improvement in oxide trap density compared to GeOx passivation.
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