Thin-Barrier Heterostructures Enabled Normally-Off Gan High Electron Mobility Transistors

In this paper, we present our recent research on the demonstration of normally-OFF operation and high-performance device merits in GaN high electron mobility transistors (HEMTs), which are enabled by the employment of thin-barrier AlGaN/GaN heterostructures. Two types of thin-barrier HEMTs are investigated: one is with a metal-oxide-semiconductor (MOS) gate structure, and the other is with a p-GaN gate stack. The MOSHEMTs feature an as-grown thin-barrier heterostructure with a gate-recess-free fabrication process and a high-k ZrO2 gate dielectric. Approaches including selective area barrier regrowth and selective area surface passivation are implemented to minimize the access resistance in the MOSHEMTs. For the p-GaN gate HEMTs, a T-shaped Schottky gate contact scheme is employed to realize superior gate stack reliability. Normally-OFF operation with a large threshold voltage 1.5 V, a high maximum drain current 450 mA mm(-1), a steep subthreshold slope 95 mV dec(-1), and negligible hysteresis are achieved in all the demonstrated device structures. Moreover, in analyzing the reported device results with the corresponding heterostructure design, we discuss the benefits and tradeoffs of thin-barrier MOSHEMTs and p-GaN gate HEMTs, respectively.