Finding an Optimal Set of Breakpoint Locations in a Control Flow Graph

With the advance of high-level synthesis methodologies it has become possible to transform software tasks, typically running on a processor, to hardware tasks running on a FPGA device. Furthermore, dynamic reconfiguration techniques allow dynamic scheduling of hardware tasks on an FPGA area at runtime. Combining these techniques allows dynamic scheduling across the hardware-software boundary. However, to interrupt and resume a task, its context has to be identified and stored. We propose a method to find an optimal set of breakpoints in the control flow of a hardware task, such that the introduced resource overhead for context access is minimized and a maximum latency between interrupt request and the end of the context storing is guaranteed. This set of breakpoints allows the context to be restricted to the essential subset of data. Our method opens the door to flexible task scheduling not only on one reconfigurable device but also between different devices and even software instances of the same task.