Standalone Rate-Distortion FME Architecture

The high computing complexity of video encoders hinders real-time throughput using a software implementation. This drawback can be amended by implementing hardware accelerators for the most computing-intensive encoder tools to achieve real-time processing while maintaining energy efficiency. In this work, we investigate how approximate and precise versions of the Fractional Motion Estimation (FME), one of the most demanding steps of modern encoders, compare in terms of hardware resources and coding efficiency. To that purpose, we designed a hardware architecture for FME targeting real-time throughput for High Definition (HD) sequences and beyond. This architecture searches over 48 candidates and, unlike most related work, uses 16-bit wide horizontal interpolated samples, which is in compliance with the High Efficiency Video Coding (HEVC) reference software. Also, it integrates all FME required computations, including the rate cost of each candidate block, what makes it a standalone FME accelerator. We analyze the impacts of our design choices in terms of coding efficiency, using software simulations, and in terms of power/energy consumption, using results obtained from standard cell synthesis.