A 112-fJ/bit 10-Gb/s Charge-Steering Equalizer Utilizing a Discrete-Time Linear Equalizer

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)(2020)

引用 1|浏览1
暂无评分
摘要
The rapid increase in the demand for low power high-frequency equalizer is triggered by the Internet-of-Things (IoT) application. Systems that operate at a high frequency usually consumes a lot of power. High power efficiency systems are more suitable for integration with devices that runs from batteries. Equalizer falls in one of two main categories; linear Continuous-Time-Linear-Equalizers (CTLE) and non-linear equalizers implemented as decision feedback equalizers (DFE). CTLE has the ability to compensate for pre-cursors a job that the DFE is unable to execute, thus both types are required to form a complete equalizer. Without proper termination, most of the input signal will be reflected back to the transmitter. Equalizer and Receiver must have a proper termination. The proposed receiver consists of a matching network flowed by four Discrete-Time-Linear-Equalizer (DTLE) and ¼ DFE. The equalizer consumes 1.12mW from a 0.9-V supply at 10 Gb/s achieving power efficiency of 112-fJ/bit with an area of 722 μm x 439 μm.
更多
查看译文
关键词
charge-steering,decision feedback equalizer,high-speed I/O,linear equalizers,receiver,serial-links
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要