An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM

Zhehong Wang,Ziyun Li,Li Xu,Qing Dong,Chin-I Su,Wen-Ting Chu,George Tsou,Yu-Der Chih,Tsung-Yung Jonathan Chang,Dennis Sylvester, Hun Seok Kim,David Blaauw

2020 IEEE SYMPOSIUM ON VLSI CIRCUITS（2020）

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摘要

We present a DNN accelerator in 22nm ULL CMOS featuring 24×1 Mb embedded RRAM. The accelerator, composed of 4 PEs and 512 MACs, achieves 0.96 TOPS/W at 120 MHz with 0.8 V VDD. Each PE contains 6 RRAM macros, equipped with a dynamic clamping offset-canceling sense amplifier that offers sub-μA current input offset.

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关键词

DNN Accelerator,RRAM,Offset Canceling Sense Amp

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