Buried Power Rail Integration with Si FinFETs for CMOS Scaling Beyond the 5 Nm Node
2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY（2020）
关键词
low resistance contact strategy,metallization,electromigration stress,CMOS scaling,FinFET,buried power rail integration,W-BPR interface,tungsten BPR lines,key scaling booster,temperature 330.0 degC,Ru
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