First Monolithic Integration Of 3d Complementary Fet (Cfet) On 300mm Wafers

S. Subramanian,M. Hosseini, T. Chiarella, S. Sarkar, P. Schuddinck, B. T. Chan, D. Radisic,G. Mannaert,A. Hikavyy, E. Rosseel,F. Sebaai,A. Peter,T. Hopf,P. Morin,S. Wang, K. Devriendt,D. Batuk,G. T. Martinez,A. Veloso,E. Dentoni Litta, S. Baudot, Y. K. Siew, X. Zhou,B. Briggs,E. Capogreco, J. Hung, R. Koret,A. Spessot,J. Ryckaert,S. Demuynck,N. Horiguchi, J. Boemmels

2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY（2020）

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摘要

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small NIP separation in a monolithic CFET results in lower parasitics and higher perfonnance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

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关键词

higher performance gains,monolithic CFET results,sequential CFET process,monolithic CFET process,3D Complementary Field Effect Transistor,3D complementary FET,monolithic integration,ultimate device footprint scaling,monolithic CFET integration scheme,NMOS nanosheet FET,functional PMOS FinFET,CFET fabrication process flow,size 300.0 mm

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