A New High-Frequency Multilevel Boost Power Factor Correction Approach With Gan Semiconductors

In this paper, a new high-frequency multilevel bridgeless boost power factor correction approach is presented. The proposed topology is a multilevel boost power factor correction circuit that significantly reduces voltage stress on switching devices, the input inductor, and the DC link capacitors. The effective switching frequency of the input current is also multiplied allowing for a significantly smaller input inductor, which improves power density. The design also reduces the voltage rating of all DC link capacitors. Additionally, the design allows access to fractional voltage levels, which can be beneficial for designs which immediately buck the DC link voltage to a lower voltage. A design example and simulation results are presented for a 100 W design and hardware results are presented for a 100 W design.