RS-LDPC Concatenated Coding for NAND Flash Memory: Designs and Reduction of Short Cycles

In NAND flash memory, the increase of Program / Erase cycles and external interference, such as electromagnetic interference and vibration, will cause various channel obstacles, including a large amount of random errors and burst errors. This work considers reliable recovery of data from such flash channels using a novel cascade of outer RS codes and inner quasi-cyclic (QC) LDPC codes. In this paper, designs and constructions of QC-LDPC code with reduction of short cycles are presented and an optimized computation cycles elimination (OCCE) algorithm is proposed. The performance of RS codes with different code rates and code lengths for concatenated codes is analyzed. Simulation results show that the decoding iterations of the QCLDPC codes in this paper compared with conventional QC-LDPC codes is reduced by up to 76% which depends on the code length of QC-LDPC at the bit error rate (BER) of 10 ^-8 . The proposed RS(273,269)-QC perform a BER of 10 ^-10 at the signal-to-noise ratio (SNR) of 3.9 dB.