An Approach to the Device-Circuit Co-Design of HyperFET Circuits

In this paper, we describe device-circuit co-design experiments for Hybrid Phase Transition FETs (HyperFETs). HyperFET transistors, built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON current without triggering the OFF current. This enables reducing supply voltage and so power consumption. HyperFETs with different ON-OFF currents tradeoffs are analyzed. Inverter chains and ring oscillators built with them are evaluated in terms of power and compared to reference designs using FETs alone. Power reductions up to 32% are shown for a HyperFET with similar OFF current and higher ON current than its FET counterpart when nodes frequently switch. However, power penalties by a factor of 400 have been obtained for other simulation stimuli. Our results identify switching activity as critical for obtaining power savings and suggest guidance both at device and circuit level to take full advantage of these devices.