Design of Higher Order Multiplier with Approximate Compressor

In recent years imprecise multiplier has been widely studied for image processing applications; this imprecise multiplier is done through compressors. For imprecise multiplication when the multiplication width is large then higher compressor adders are used to reduce the reduction stage. The challenging task in higher compressor approximation via truth table, K-map is impossible. In this paper, the 8:2 compressor is designed and a novel comparison technique is developed for approximation. The proposed 8:2 compressor is used in 16x16 multiplier and compared with existing multiplier. The new novel compressor is efficient in area, power, and delay. Another performance characteristic of error distance (ED) and normalized error distance (NED) is compared between related works. The proposed multiplier used in image multiplication then the PSNR is compared.