Bias stress instability of LTPS TFTs on flexible substrate with activation annealing temperature

In this paper, we identified the defect state of p-channel low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate that is distributed differently in the interface and channel areas depending on the activation annealing temperature, as well as observed the effect on the threshold voltage (VT) and reliability. To verify the effect of the process temperature on the performance of the LTPS TFTs, an activation heat treatment was conducted at 400 °C, 370 °C and 340 °C. More defects were distributed in the interface and channel area of LTPS TFTs with low heat treatment temperature, resulting in VT formed at a higher voltage. After the negative bias temperature instability (NBTI) test, the VT shifted in the negative voltage direction and moved −0.13 V, −0.51 V and −0.72 V from LTPS TFTs with high activation annealing temperature. In the hot carrier instability (HCI) test, VT also shifted to the negative direction of −0.19 V, −0.51 V, and −1.07 V. The defects distributed in the interface and channel areas that are not curated or activated due to the low activation annealing temperature caused instability under the bias stress.